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    Your email address will not be published. The total cell area includes just the standard cells, while the total area can include interconnect area as well. If available, we will want to use the total area in our analysis. Otherwise we can just use the cell area. This is one reason we try not to flatten our designs, since the module hierarchy helps us understand the area breakdowns. If we completely flattened the design there would only be one line in the above table. Note that this power analysis is actually not that useful yet, since at this stage of the flow the power analysis is based purely on statistical activity factor estimation.

    This is a pretty poor estimate, so we should never use this kind of statistical power estimation in this course. Take a few minutes to examine the resulting Verilog gate-level netlist. Notice that the module hierarchy is preserved and also notice that the MinMaxUnit synthesizes into a large number of basic logic gates. We can use the Synopsys Design Vision DV tool for browsing the resulting gate-level netlist, plotting critical path histograms, and generally analyzing our design.

    You can then use the following steps to view the gate-level schematic for the MinMaxUnit :. This shows you the exact gates used to implement the MinMaxUnit. You can use the following steps to view a histogram of path slack, and also to open a gave-level schematic of just the critical path. This shows you the exact gates that lie on the critical path.

    Notice that there nine levels of logic including the registers on the critical path. If there are just a few levels of logic on the critical path then our design is probably very simple as in this case! The following screen capture illutrates using Design Vision to explore the post-synthesis results. While this can be interesting, in this course, we almost always prefer exploring the post-place-and-route results, so we will not really use Synopsys DC that often. To Do On Your Own: Sweep a range of target clock frequencies to determine the shortest possible clock period which still meets timing without any negative slack.

    You can put a sequence of commands in a. So consider placing the commands from this section into a. Then gradually increase the clock period until your design meets timing. To follow along with the tutorial, push the design through synth again using 0. Before synthesis, we used Synopsys VCS to do a 4-state simulation. Gate-level simulation provides an advantage over RTL simulation because it more precisely represents the specification of the true hardware generated by the tools.

    Notice there are some differences in the vcs command we ran here, and the one we ran for 4-state RTL simulation. In this version, we use the gate-level netlist post-synth. This is similar to RTL simulation, and you should notice that all signals will change on the clock edge. We use Cadence Innovus for placing standard cells in rows and then automatically routing all of the nets between these standard cells. We also use Cadence Innovus to route the power and ground rails in a grid and connect this grid to the power and ground pins of each standard cell, and to automatically generate a clock tree to distribute the clock to all sequential state elements with hopefully low skew.

    We will be running Cadence Innovus in a separate directory to keep the files separate from the other tools. Before starting Cadence Innovus, we need two files which will be loaded into the tool. The first file is a. This file is where we specify our target clock period, but it is also where we could specify input or output delay constraints e.

    We created this file at the end of our synthesis step using Synopsys DC. In this case, we are targeting a 1. Note that we also see the constraints that we set for input and output delay, max fanout, max transition as well as our path groups. A corner is a characterization of the standard cell library and technology with specific assumptions about the process, temperature, and voltage PVT. To ensure our design will work across a range of operating conditions, we need to evaluate our design across a range of corners.

    Use Geany or your favorite text editor to create a file named setup-timing. This file includes information about the resistance and capacitance of every metal layer. In this specific example, we are creating a typical corner by putting together the typical. Now that we have created our setup-timing. As we enter commands we will be able use the GUI to see incremental progress towards a fully placed-and-routed design.

    We need to set various variables before starting to work in Cadence Innovus. These variables tell Cadence Innovus the location of the MMMC file, the location of the Verilog gate-level netlist, the name of the top-level module in our design, the location of the. Then, we tell innovus the type of timing analysis we want it to do. In on-chip variation OCV mode, the software calculates clock and data path delays based on minimum and maximum operating conditions for setup analysis and vice-versa for hold analysis.

    These delays are used together in the analysis of each check. The OCV is the small difference in the operating parameter value across the chip. Each timing arc in the design can have an early and a late delay to account for the on-chip process, voltage, and temperature variation. We need this mode in order to do proper hold time fixing later on.

    The next step is to do some floorplaning. This is where we broadly organize the chip in terms of its overall dimensions and the placement of any previously designed blocks. For now we just do some very simple floorplanning using the floorPlan command. In this example, we have chosen the aspect ratio to be 1. If the cell utilization is too high, Cadence Innovus will spend way too much time trying to optimize the design and will eventually simply give up. We have also added 4.

    The following screen capture illustrates what you should see: a square floorplan with rows where the standard cells will eventually be placed. The next step is to work on power routing. Recall that each standard cell has internal M1 power and ground rails which will connect via abutment when the cells are placed into rows. If we were just to supply power to cells using these rails we would likely have large IR drop and the cells in the middle of the chip would effectively be operating at a much lower voltage.

    During power routing, we create a grid of power and ground wires on the top metal layers and then connect this grid down to the M1 power rails in each row. We also create a power ring around the entire floorplan. Before doing the power routing, we need to use the globalNetCommand command to tell Cadence Innovus which nets are power and which nets are ground there are many possible names for power and ground!

    We now create a power ring around our chip using the addRing command. A power ring ensures we can easily get power and ground to all standard cells. The command takes parameters specifying the width of each wire in the ring, the spacing between the two rings, and what metal layers to use for the ring. These top layers have high capacitance but this is not an issue since the power and ground rails are not switching and indeed this extra capacitance can serve as a very modest amount of decoupling capacitance to smooth out time variations in the power supply.

    We have power and ground rails along each row of standard cells and a power ring, so now we need to hook these up. We can use the addStripe command to draw wires and automatically insert vias whenever wires cross. The following screen capture illustrates what you should see: a power ring and grid on M6 and M7 connected to the horizontal power and ground rails on M1.

    You can toggle the visibility of metal layers by using the panel on the right. Click the checkbox in the V column to toggle the visibility of the corresponding layer. You can also simply use the number keys on your keyboard. Pressing the 6 key will toggle M6 and pressing the 7 key will toggle M7.

    Zoom in on a via and toggle the visibility of the metal layers to see how Cadence Innovus has automatically inserted a via stack that goes from M1 all the way up to M6 or M7. The following screen capture illustrates what you should see: the gates have been placed underneath a sea of wiring on the various metal layers. Note that Cadence Innovus has only done a very preliminary routing, primarily to help improve placement.

    You can use the Amobea workspace to help visualize how modules are mapped across the chip. However, we recommend using the design browser to help visualize how modules are mapped across the chip. Here are the steps:. In this way you can view where various modules are located on the chip. The following screen capture illustrates the location of the five MinMaxUnit modules.

    Notice how Cadence Innovus has grouped each module together. The placement algorithm tries to keep connected standard cells close together to minimize wiring. The next step is to assign IO pin location for our block-level design. The next step is to improve the quality of the clock tree routing. In the right panel click on Net and then deselect the checkbox in the V column next to Signal , Special Net , Power , and Ground so that only Clock is selected.

    You should be able to see the clock snaking around the chip connecting the clock port of all of the registers. If you watch closely you should see a significant difference in the clock tree routing before and after optimization. The following screen capture illustrates the optimized clock tree routing.

    The routes are straighter, shorter, and well balanced. This will result in much lower clock skew. To avoid hold time violations situations where the contamination delay is smaller than the hold time and new data arrives too quickly we include the following commands:. Here, we specified a list of buffer cells to the tool from stdcells.

    We then tell innovus our hold and setup time constraints, in nanoseconds, these numbers were derived from the. Then, we actually fix any violating paths using the optDesign command. This means that as a result of our hold time optimization, we have added 51 buffer cells to the netlist. The next step is to improve the quality of the signal routing.

    Display just the signals but not the power and ground routing by clicking on the checkbox in the V column next to Signal in the left panel. Then use the routeDesign command to optimize the signal routing. We follow this with another iteration of optDesign to fix any violating paths that were created during routeDesign.

    If you watch closely you should see a significant difference in the signal routing before and after optimization. The following screen capture illustrates the optimized signal routing. Again the routes are straighter and shorter. This will reduce the interconnect resistance and capacitance and thus improve the delay and energy of our design.

    Filler cells are essentially empty standard cells whose sole purpose is to connect the wells across each standard cell row. Zoom in to see some of the detailed routing and take a moment to appreciate how much effort the tools have done for us automatically to synthesize, place, and route this design. The following screen capture shows some of this detailed routing.

    Notice how each metal layer always goes in the same direction. So M2 is always vertical, M3 is always horizontal, M4 is always vertical, etc. This helps reduce capacitive coupling across layers and also simplifies the routing algorithm. This is an example of the sophisticated algorithms used in these tools.

    Our design is now on silicon! Obviously there are many more steps required before you can really tape out a chip. For example, one thing we want to do is verify that the gate-level netlist matches what is really in the final layout. We can do this using the verifyConnectivity command. Now we can generate various output files. We might want to save the final gate-level netlist for the chip, since Cadence Innovus will often insert new cells or change cells during its optimization passes.

    We can also extract resistance and capacitance for the metal interconnect and write this to a special. You may get an error regarding open nets. This is actually more of a warning message, and for the purposes of RC extraction we can ignore this.

    We also need to extract delay information and write this to an. Finally, we of course need to generate the real layout as a. This is what we will send to the foundry when we are ready to tapeout the chip. We can also use Cadence Innovus to do timing, area, and power analysis similar to what we did with Synopsys DC. These post-place-and-route results will be much more accurate than the preliminary post-synthesis results.

    Note that for these results we used a target clock period of 0. This was the shortest clock period which still met timing without any negative slack during synthesis. From the above report we can see that our design is still meeting timing even after place-and-route. Note that it is very likely that the critical path identified by Synsopsys DC after synthesis will not be the same critical path identified by Cadence Innovus after place-and-route.

    This is because Synopsys DC can only guess the final placement of the cells and interconnect during static timing analysis, while Cadence Innovus can use the real placement of the cells and interconnect during static timing analysis. For the same reason, there is no guarantee that if your design meets timing after synthesis that it will still meet timing after place-and-route! It is very possible that your design will meet timing after synthesis and then will not meet timing after place-and-route.

    If your design does not meet timing after place-and-route you must go back and use a longer target clock period for synthesis! You can use the following steps in Cadence Innovus to display where the critical path is on the actual chip. You can also use the Design Browser to highlight specific modules to visualize how the critical path is routed across the chip between these modules.

    The following screen capture illustrates the critical path in our three-stage sort unit. Cadence Innovus has worked hard in both placement and routing to keep the critical path short. If your critical path stretches across the entire chip you may need to take extra steps such as explicit floorplanning or hierarchical design to help the tools produce a better quality of result. These area results will be far more accurate than the post-synthesis results.

    The Inst column indicates the number of non-filler cells in that module. There are a total of standard cells in the design. Each register has eight standard cells; eight flip-flops since it is an eight-bit register. The MinMaxUnit s have a different number of cells since they have been optimized differently.

    Note that this power analysis is still not that useful yet, since at this stage of the flow the power analysis is still based purely on statistical activity factor estimation. We will do more realistic power analysis in the next section. We can now look at the actual. Zoom in and out to see the individual transistors as well as the entire chip.

    The following screen capture illutrates using Klayout to view the layout for the entire sort unit. The following figure shows a zoomed portion of the layout. You can clearly see the active layer inside the standard cells along with the signal routing on the lower metal layers. The power routing on the upper metal layers has been hiddent for clarity.

    For example, experiment with a sort unit capable of sorting bit or bit values. You will need to adjust the test harness and simulation driver appropriately. Before place and route, we used Synopsys VCS to do 4-state simulation, and gate-level simulation.

    This means that running a back-annotated simulation with a cycle time that is too fast will cause the design to fail! Back-annotated simulations are also useful for detecting hold-time violations. Given the more realistic timing implications of a back-annotated simulation, we need to be more careful about the cycle time, input delay, and output delay that we provide to vcs. Notice the differences between this command and the fast functional gate-level simulation command:.

    Negative values in timing checks are important for cells which have negative hold times, for example. These values are based on the input and output delays we set during the Synopsys DC synthesis step which you might recall was 0. Note that we assert the value at the clock constraint minus the output delay.

    This ensures that the signal arrives and is stable by a margin of the output delay. Including these macros will ensure that our timing checks will actually mean something. Without this, our simulations may pass because data arrives before the clock edge, even if it does not arrive before the output delay. In such a case, the timing checks will be completely bogus.

    To illustrate how useful these timing checks can be, lets run another simulation where we try to push the design to run too quickly. Here, we reduce the cycle time down to 0. Note that we also annotated the sdf using the maximum delays, due to the -sdf max It is important to do a check using the maximum delays for setup time checks, and using minimum delays for hold time checks. Here, we can see the violating flip-flop, and the subsequent testbench failure.

    Note that you resulting netlist and layout may be slightly different than the one referenced here, so if your timing violation looks slightly different, or you do not yet have a timing violation, that is ok! This can make these. For average power analysis, we only need to know the activity factor on each net. We can use the vcd2saif tool to convert. Take a look at the vcd file from this simulation. Here we can see some subcycle delays that shows us how long it takes for data to stabilize before the following cycle, super cool!

    This is showing the first stage of the sort unit pipeline. There are many ways to perform power analysis. As mentioned earlier, the post-synthesis and post-place-and-route power reports use statistical power analysis where we simply assume some toggle probability on each net. For more accurate power analysis we need to find out the actual activity for every net for a given experiment.

    One way to do this is to perform post-place-and-route gate-level simulation. Since Synopsys PT is primarily used for static timing analysis, we need to explicitly tell Synopsys PT that we want to use it for power analysis. We now read in the gate-level netlist, tell Synopsys PT we want to do power analysis for the top-level module, and link the design i. In order to do power analysis, Synopsys PT needs to know the clock period.

    Here we will set the clock frequency to be the same as the initial clock constraint, but note that this is only valid if our design actually met timing. If our design has negative slack, then this means we cannot actually run the design at the target clock frequency and we will need to iterate to meet timing. We are now ready to read in the actual activity factors which will be used for power analysis. We need to strip off part of the instance names in the.

    Recall that we used Cadence Innovus to generate exactly this information in a. So we now read in these additional parasitic capacitance values for every net in the gate-level netlist. These numbers are in Watts. Power is the rate change of energy i. When we ran the sort unit simulator at the beginning of the tutorial, we saw that the simulation required cycles. Assuming our sort unit runs as 0. Since we are doing sorts, this corresponds to about 1pJ per sort. The power is broken down into internal, switching, and leakage power.

    Internal and switching power are both forms of dynamic power, while leakage power is a form of static power. Notice that in this case, the dynamic power is much more significant than the static power. Internal power was described earlier in this tutorial, so you may want to revisit that section. Note that internal power includes short circuit power, but it can also include the local clock power internal to the cell. In this overview, the power is also broken down by the power consumed in the global clock network, registers, and combinational logic.

    Switching power is the power dissipated by the charging and discharging of the load capacitance at the output of each cell.

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